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lm5112 www.ti.com snvs234b ? september 2004 ? revised april 2006 lm5112 tiny 7a mosfet gate driver check for samples: lm5112 1 features description the lm5112 mosfet gate driver provides high peak 2 ? compound cmos and bipolar outputs reduce gate drive current in the tiny wson-6 package (sot- output current variation 23 equivalent footprint) or an 8-lead exposed-pad ? 7a sink/3a source current msop package, with improved power dissipation ? fast propagation times (25 ns typical) required for high frequency operation. the compound output driver stage includes mos and bipolar ? fast rise and fall times (14 ns/12 ns rise/fall transistors operating in parallel that together sink with 2 nf load) more than 7a peak from capacitive loads. combining ? inverting and non-inverting inputs provide the unique characteristics of mos and bipolar either configuration with a single device devices reduces drive current variation with voltage and temperature. under-voltage lockout protection is ? supply rail under-voltage lockout protection provided to prevent damage to the mosfet due to ? dedicated input ground (in_ref) for split insufficient gate turn-on voltage. the lm5112 supply or single supply operation provides both inverting and non-inverting inputs to ? power enhanced 6-pin wson package (3.0mm satisfy requirements for inverting and non-inverting x 3.0mm) or thermally enhanced msop- gate drive with a single device type. powerpad package ? output swings from v cc to v ee which can be negative relative to input ground block diagram figure 1. block diagram of lm5112 1 please be aware that an important notice concerning availability, standard warranty, and use in critical applications of texas instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. 2 all trademarks are the property of their respective owners. production data information is current as of publication date. copyright ? 2004 ? 2006, texas instruments incorporated products conform to specifications per the terms of the texas instruments standard warranty. production processing does not necessarily include testing of all parameters. v ee out in inb in_ref uvlo v cc level shift
lm5112 snvs234b ? september 2004 ? revised april 2006 www.ti.com pin configurations figure 2. wson-6 figure 3. msop-powerpad-8 pin descriptions pin name description application information wson-6 msop-8 1 4 in non-inverting input pin ttl compatible thresholds. pull up to vcc when not used. 2 3 vee power ground for driver outputs connect to either power ground or a negative gate drive supply for positive or negative voltage swing. 3 6 vcc positive supply voltage input locally decouple to vee. the decoupling capacitor should be located close to the chip. 4 7 out gate drive output capable of sourcing 3a and sinking 7a. voltage swing of this output is from vee to vcc. 5 1 in_ref ground reference for control inputs connect to power ground (vee) for standard positive only output voltage swing. connect to system logic ground when vee is connected to a negative gate drive supply. 6 2 inb inverting input pin ttl compatible thresholds. connect to in_ref when not used. - - - 5, 8 n/c not internally connected - - - - - - exposed exposed pad, underside of package internally bonded to the die substrate. connect to vee pad ground pin for low thermal impedance. these devices have limited built-in esd protection. the leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the mos gates. 2 submit documentation feedback copyright ? 2004 ? 2006, texas instruments incorporated product folder links: lm5112 1 2 3 4 5 6 in out in_ref inb vcc vee inb vee in out vcc n/c n/c in_ref 1 2 3 4 8 7 6 5
lm5112 www.ti.com snvs234b ? september 2004 ? revised april 2006 absolute maximum ratings (1) (2) v cc to v ee ? 0.3v to 15v v cc to in_ref ? 0.3v to 15v in/inb to in_ref ? 0.3v to 15v in_ref to v ee ? 0.3v to 5v storage temperature range ? 55 c to +150 c maximum junction temperature +150 c operating junction temperature ? 40 c+125 c esd rating 2kv (1) absolute maximum ratings are limits beyond which damage to the device may occur. operating ratings are conditions under which operation of the device is intended to be functional. for ensured specifications and test conditions, see the electrical characteristics. (2) if military/aerospace specified devices are required, please contact the texas instruments sales office/ distributors for availability and specifications. electrical characteristics t j = ? 40 c to +125 c, v cc = 12v, inb = in_ref = v ee = 0v, no load on output, unless otherwise specified. symbol parameter conditions min typ max units supply v cc v cc operating range v cc ? in_ref and v cc - v ee 3.5 14 v uvlo v cc under-voltage lockout (rising) v cc ? in_ref 2.4 3.0 3.5 v v cch v cc under-voltage hysteresis 230 mv i cc v cc supply current 1.0 2.0 ma control inputs v ih logic high 2.3 v v il logic low 0.8 v v thh high threshold 1.3 1.75 2.3 v v thl low threshold 0.8 1.35 2.0 v hys input hysteresis 400 mv i il input current low in = inb = 0v -1 0.1 1 a i ih input current high in = inb = v cc -1 0.1 1 a output driver r oh output resistance high i out = -10ma (1) 30 50 ? r ol output resistance low i out = 10ma (1) 1.4 2.5 ? i source peak source current out = v cc /2, 200ns pulsed current 3 a i sink peak sink current out = v cc /2, 200ns pulsed current 7 a (1) the output resistance specification applies to the mos device only. the total output current capability is the sum of the mos and bipolar devices. copyright ? 2004 ? 2006, texas instruments incorporated submit documentation feedback 3 product folder links: lm5112
lm5112 snvs234b ? september 2004 ? revised april 2006 www.ti.com electrical characteristics (continued) t j = ? 40 c to +125 c, v cc = 12v, inb = in_ref = v ee = 0v, no load on output, unless otherwise specified. symbol parameter conditions min typ max units switching characteristics td1 propagation delay time low to high, c load = 2 nf, see figure 4 and 25 40 ns in/ inb rising ( in to out) figure 5 td2 propagation delay time high to low, c load = 2 nf, see figure 4 and 25 40 ns in / inb falling (in to out) figure 5 tr rise time c load = 2 nf, see figure 4 and 14 ns figure 5 tf fall time c load = 2 nf, see figure 4 and 12 ns figure 5 latchup protection aec ? q100, method 004 t j = 150 c 500 ma thermal resistance ja junction to ambient, wson-6 package 40 c/w 0 lfpm air flow msop-powerpad package 60 jc junction to case wson-6 package 7.5 c/w msop-powerpad package 4.7 timing waveforms figure 4. inverting figure 5. non-inverting 4 submit documentation feedback copyright ? 2004 ? 2006, texas instruments incorporated product folder links: lm5112 inb output t f t d1 t r t d2 90% 10% 50% 50% in output t r t d1 t f t d2 90% 10% 50% 50%
lm5112 www.ti.com snvs234b ? september 2004 ? revised april 2006 typical performance characteristics supply current supply current vs vs frequency capacitive load figure 6. figure 7. rise and fall time rise and fall time vs vs supply voltage temperature figure 8. figure 9. rise and fall time delay time vs vs capacitive load supply voltage figure 10. figure 11. copyright ? 2004 ? 2006, texas instruments incorporated submit documentation feedback 5 product folder links: lm5112 v cc = 15v v cc = 10v v cc = 5v t a = 25c c l = 2200pf 0.1 1 10 100 supply current (ma) 1 10 100 1000 frequency (khz) f = 500khz f = 100khz f = 10khz t a = 25c v cc = 12v supply current (ma) 1 100 0.1 10 100 1k 10k capacitive load (pf) 17.5 20 22.5 25 27.5 30 32.5 time (ns) 4 6 8 10 12 14 16 supply voltage (v) t a = 25c c l = 2200pf t d2 t d1 0 10 20 30 40 50 time (ns) 100 1k 10k capacitive load (pf) t r t f t a = 25c v cc = 12v 10 14 16 18 20 time (ns) 12 4 6 9 10 12 13 16 supply voltage (v) 5 7 8 11 14 15 t r t f t a = 25c c l = 2200pf -75 -50 -25 0 25 50 75 100 125 150 175 temperature (c) 8 10 12 14 16 18 time (ns) t r t f v cc = 12v c l = 2200pf
lm5112 snvs234b ? september 2004 ? revised april 2006 www.ti.com typical performance characteristics (continued) delay time rdson vs vs temperature supply voltage figure 12. figure 13. uvlo thresholds and hysteresis peak current vs vs temperature supply voltage figure 14. figure 15. 6 submit documentation feedback copyright ? 2004 ? 2006, texas instruments incorporated product folder links: lm5112 1.7 2.0 2.3 2.6 2.9 3.2 uvlo thresholds (v) -75 -50 -25 0 25 50 75 100 125 150 175 temperature (c) 0.150 0.210 0.270 0.330 0.450 0.390 hysteresis ( v ) v cc - falling hysteresis v cc - rising 15 supply voltage (v) current (a) source 5 7 9 11 13 0 1 2 3 4 5 6 7 8 sink t a = 25c v out = 5v 0.75 1.25 1.75 2.25 2.75 3.25 r ol ( : ) 0 3 6 9 12 15 18 supply voltage (v) 15 25 45 55 65 35 r oh ( : ) r oh r ol t a = 25c i out = 10ma 17.5 20 22.5 25 27.5 30 32.5 time (ns) 35 -75 -50 -25 0 25 50 75 100 125 150 175 temperature (c) t d2 t d1 v cc = 12v c l = 2200pf
lm5112 www.ti.com snvs234b ? september 2004 ? revised april 2006 simplified application block diagram figure 16. simplified application block diagram detailed operating description the lm5112 is a high speed , high peak current (7a) single channel mosfet driver. the high peak output current of the lm5112 will switch power mosfet ? s on and off with short rise and fall times, thereby reducing switching losses considerably. the lm5112 includes both inverting and non-inverting inputs that give the user flexibility to drive the mosfet with either active low or active high logic signals. the driver output stage consists of a compound structure with mos and bipolar transistor operating in parallel to optimize current capability over a wide output voltage and operating temperature range. the bipolar device provides high peak current at the critical miller plateau region of the mosfet v gs , while the mos device provides rail-to-rail output swing. the totem pole output drives the mosfet gate between the gate drive supply voltage v cc and the power ground potential at the v ee pin. the control inputs of the driver are high impedance cmos buffers with ttl compatible threshold voltages. the negative supply of the input buffer is connected to the input ground pin in_ref. an internal level shifting circuit connects the logic input buffers to the totem pole output drivers. the level shift circuit and separate input/output ground pins provide the option of single supply or split supply configurations. when driving the mosfet gates from a single positive supply, the in_ref and v ee pins are both connected to the power ground. the isolated input and output stage grounds provide the capability to drive the mosfet to a negative v gs voltage for a more robust and reliable off state. in split supply configuration, the in_ref pin is connected to the ground of the controller which drives the lm5112 inputs. the v ee pin is connected to a negative bias supply that can range from the in_ref potential to as low as 14 v below the vcc gate drive supply. for reliable operation, the maximum voltage difference between v cc and in_ref or between v cc and v ee is 14v. copyright ? 2004 ? 2006, texas instruments incorporated submit documentation feedback 7 product folder links: lm5112 lm5025 controller fb out_a out_b -3v inb in_a in_ref in inb lm5110-1 out_b out_a v cc v ee v ee out v ee in_ref v out v in +5v dual supply utilizing negative output voltage drive lm5112 v cc +10v uvlo in_ref in_ref
lm5112 snvs234b ? september 2004 ? revised april 2006 www.ti.com the minimum recommended operating voltage between vcc and in_ref is 3.5v. an under voltage lock out (uvlo) circuit is included in the lm5112 which senses the voltage difference between v cc and the input ground pin, in_ref. when the v cc to in_ref voltage difference falls below 2.8v the driver is disabled and the output pin is held in the low state. the uvlo hysteresis prevents chattering during brown-out conditions; the driver will resume normal operation when the v cc to in_ref differential voltage exceeds 3.0v. layout considerations attention must be given to board layout when using lm5112. some important considerations include: 1. a low esr/esl capacitor must be connected close to the ic and between the v cc and v ee pins to support high peak currents being drawn from v cc during turn-on of the mosfet. 2. proper grounding is crucial. the driver needs a very low impedance path for current return to ground avoiding inductive loops. two paths for returning current to ground are a) between lm5112 in_ref pin and the ground of the circuit that controls the driver inputs and b) between lm5112 v ee pin and the source of the power mosfet being driven. both paths should be as short as possible to reduce inductance and be as wide as possible to reduce resistance. these ground paths should be distinctly separate to avoid coupling between the high current output paths and the logic signals that drive the lm5112. with rise and fall times in the range of 10 to 30nsec, care is required to minimize the lengths of current carrying conductors to reduce their inductance and emi from the high di/dt transients generated when driving large capacitive loads. 3. if either channel is not being used, the respective input pin (in or inb) should be connected to either v ee or v cc to avoid spurious output signals. thermal performance introduction the primary goal of the thermal management is to maintain the integrated circuit (ic) junction temperature (tj) below a specified limit to ensure reliable long term operation. the maximum t j of ic components should be estimated in worst case operating conditions. the junction temperature can be calculated based on the power dissipated on the ic and the junction to ambient thermal resistance ja for the ic package in the application board and environment. the ja is not a given constant for the package and depends on the pcb design and the operating environment. drive power requirement calculations in lm5112 lm5112 is a single low side mosfet driver capable of sourcing / sinking 3a / 7a peak currents for short intervals to drive a mosfet without exceeding package power dissipation limits. high peak currents are required to switch the mosfet gate very quickly for operation at high frequencies. the schematic above shows a conceptual diagram of the lm5112 output and mosfet load. q1 and q2 are the switches within the gate driver. rg is the gate resistance of the external mosfet, and cin is the equivalent gate capacitance of the mosfet. the equivalent gate capacitance is a difficult parameter to measure as it is the combination of cgs (gate to source capacitance) and cgd (gate to drain capacitance). the cgd is not a constant and varies with the drain voltage. the better way of quantifying gate capacitance is the gate charge qg in coloumbs. qg combines the charge required by cgs and cgd for a given gate drive voltage vgate. the gate resistance rg is usually very small and losses in it can be neglected. the total power dissipated in the mosfet driver due to gate charge is approximated by: p driver = v gate x q g x f sw 8 submit documentation feedback copyright ? 2004 ? 2006, texas instruments incorporated product folder links: lm5112 v high q2 v gate r g q1 v trig c in
lm5112 www.ti.com snvs234b ? september 2004 ? revised april 2006 where ? f sw = switching frequency of the mosfet (1) for example, consider the mosfet mtd6n15 whose gate charge specified as 30 nc for v gate = 12v. therefore, the power dissipation in the driver due to charging and discharging of mosfet gate capacitances at switching frequency of 300 khz and v gate of 12v is equal to p driver = 12v x 30 nc x 300 khz = 0.108w. (2) in addition to the above gate charge power dissipation, - transient power is dissipated in the driver during output transitions. when either output of the lm5112 changes state, current will flow from v cc to v ee for a very brief interval of time through the output totem-pole n and p channel mosfets. the final component of power dissipation in the driver is the power associated with the quiescent bias current consumed by the driver input stage and under-voltage lockout sections. characterization of the lm5112 provides accurate estimates of the transient and quiescent power dissipation components. at 300 khz switching frequency and 30 nc load used in the example, the transient power will be 8 mw. the 1 ma nominal quiescent current and 12v v gate supply produce a 12 mw typical quiescent power. therefore the total power dissipation p d = 0.118 + 0.008 + 0.012 = 0.138w. (3) we know that the junction temperature is given by t j = p d x ja + t a (4) or the rise in temperature is given by t rise = t j ? t a = p d x ja (5) for wson-6 package, the integrated circuit die is attached to leadframe die pad which is soldered directly to the printed circuit board. this substantially decreases the junction to ambient thermal resistance ( ja ). by providing suitable means of heat dispersion from the ic to the ambient through exposed copper pad, which can readily dissipate heat to the surroundings, ja as low as 40 c / watt is achievable with the package. the resulting trise for the driver example above is thereby reduced to just 5.5 degrees. therefore t rise is equal to t rise = 0.138 x 40 = 5.5 c (6) for msop-powerpad ja is typically 60 c/w. copyright ? 2004 ? 2006, texas instruments incorporated submit documentation feedback 9 product folder links: lm5112
package option addendum www.ti.com 2-oct-2014 addendum-page 1 packaging information orderable device status (1) package type package drawing pins package qty eco plan (2) lead/ball finish (6) msl peak temp (3) op temp (c) device marking (4/5) samples lm5112my/nopb active msop- powerpad dgn 8 1000 green (rohs & no sb/br) cu sn level-1-260c-unlim sjjb lm5112myx/nopb active msop- powerpad dgn 8 3500 green (rohs & no sb/br) cu sn level-1-260c-unlim sjjb lm5112q1sd/nopb active wson ngg 6 1000 green (rohs & no sb/br) cu sn level-1-260c-unlim -40 to 125 l250b lm5112q1sdx/nopb active wson ngg 6 4500 green (rohs & no sb/br) cu sn level-1-260c-unlim -40 to 125 l250b lm5112sd nrnd wson ngg 6 1000 tbd call ti call ti -40 to 125 l132b lm5112sd/nopb active wson ngg 6 1000 green (rohs & no sb/br) cu nipdau | cu sn level-1-260c-unlim -40 to 125 l132b lm5112sdx nrnd wson ngg 6 4500 tbd call ti call ti -40 to 125 l132b lm5112sdx/nopb active wson ngg 6 4500 green (rohs & no sb/br) cu nipdau | cu sn level-1-260c-unlim -40 to 125 l132b (1) the marketing status values are defined as follows: active: product device recommended for new designs. lifebuy: ti has announced that the device will be discontinued, and a lifetime-buy period is in effect. nrnd: not recommended for new designs. device is in production to support existing customers, but ti does not recommend using this part in a new design. preview: device has been announced but is not in production. samples may or may not be available. obsolete: ti has discontinued the production of the device. (2) eco plan - the planned eco-friendly classification: pb-free (rohs), pb-free (rohs exempt), or green (rohs & no sb/br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. tbd: the pb-free/green conversion plan has not been defined. pb-free (rohs): ti's terms "lead-free" or "pb-free" mean semiconductor products that are compatible with the current rohs requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. where designed to be soldered at high temperatures, ti pb-free products are suitable for use in specified lead-free processes. pb-free (rohs exempt): this component has a rohs exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. the component is otherwise considered pb-free (rohs compatible) as defined above. green (rohs & no sb/br): ti defines "green" to mean pb-free (rohs compatible), and free of bromine (br) and antimony (sb) based flame retardants (br or sb do not exceed 0.1% by weight in homogeneous material) (3) msl, peak temp. - the moisture sensitivity level rating according to the jedec industry standard classifications, and peak solder temperature. (4) there may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
package option addendum www.ti.com 2-oct-2014 addendum-page 2 (5) multiple device markings will be inside parentheses. only one device marking contained in parentheses and separated by a "~" will appear on a device. if a line is indented then it is a continuation of the previous line and the two combined represent the entire device marking for that device. (6) lead/ball finish - orderable devices may have multiple material finish options. finish options are separated by a vertical ruled line. lead/ball finish values may wrap to two lines if the finish value exceeds the maximum column width. important information and disclaimer: the information provided on this page represents ti's knowledge and belief as of the date that it is provided. ti bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. efforts are underway to better integrate information from third parties. ti has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. ti and ti suppliers consider certain information to be proprietary, and thus cas numbers and other limited information may not be available for release. in no event shall ti's liability arising out of such information exceed the total purchase price of the ti part(s) at issue in this document sold by ti to customer on an annual basis. other qualified versions of lm5112, LM5112-Q1 : ? catalog: lm5112 ? automotive: LM5112-Q1 note: qualified version definitions: ? catalog - ti's standard catalog product ? automotive - q100 devices qualified for high-reliability automotive applications targeting zero defects
tape and reel information *all dimensions are nominal device package type package drawing pins spq reel diameter (mm) reel width w1 (mm) a0 (mm) b0 (mm) k0 (mm) p1 (mm) w (mm) pin1 quadrant lm5112my/nopb msop- power pad dgn 8 1000 178.0 12.4 5.3 3.4 1.4 8.0 12.0 q1 lm5112myx/nopb msop- power pad dgn 8 3500 330.0 12.4 5.3 3.4 1.4 8.0 12.0 q1 lm5112q1sd/nopb wson ngg 6 1000 178.0 12.4 3.3 3.3 1.0 8.0 12.0 q1 lm5112q1sdx/nopb wson ngg 6 4500 330.0 12.4 3.3 3.3 1.0 8.0 12.0 q1 lm5112sd wson ngg 6 1000 178.0 12.4 3.3 3.3 1.0 8.0 12.0 q1 lm5112sd/nopb wson ngg 6 1000 180.0 12.4 3.3 3.3 1.0 8.0 12.0 q1 lm5112sdx wson ngg 6 4500 330.0 12.4 3.3 3.3 1.0 8.0 12.0 q1 lm5112sdx/nopb wson ngg 6 4500 330.0 12.4 3.3 3.3 1.0 8.0 12.0 q1 package materials information www.ti.com 31-jan-2015 pack materials-page 1
*all dimensions are nominal device package type package drawing pins spq length (mm) width (mm) height (mm) lm5112my/nopb msop-powerpad dgn 8 1000 210.0 185.0 35.0 lm5112myx/nopb msop-powerpad dgn 8 3500 367.0 367.0 35.0 lm5112q1sd/nopb wson ngg 6 1000 210.0 185.0 35.0 lm5112q1sdx/nopb wson ngg 6 4500 367.0 367.0 35.0 lm5112sd wson ngg 6 1000 210.0 185.0 35.0 lm5112sd/nopb wson ngg 6 1000 203.0 203.0 35.0 lm5112sdx wson ngg 6 4500 367.0 367.0 35.0 lm5112sdx/nopb wson ngg 6 4500 346.0 346.0 35.0 package materials information www.ti.com 31-jan-2015 pack materials-page 2
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